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64-macrocell max? epld cy7c343 cypress semiconductor corporation 3901 north first street san jose ca 95134 408-943-2600 july 18, 2000 features ? 64 max macrocells in 4 labs 8 dedicated inputs, 24 bidirectional i/o pins programmable interconnect array 0.8-micron double-metal cmos eprom technology available in 44-pin hlcc, plcc lowest power max device functional description the cy7c343 is a high-performance, high-density erasable programmable logic device, available in 44-pin plcc and hlcc packages. the cy7c343 contains 64 highly flexible macrocells and 128 expander product terms. these resources are divided into four logic array blocks (labs) connected through the programma- ble inter-connect array (pia). there are 8 input pins, one that doubles as a clock pin when needed. the cy7c343 also has 28 i/o pins, each connected to a macrocell (6 for labs a and c, and 8 for labs b and d). the remaining 36 macrocells are used for embedded logic. the cy7c343 is excellent for a wide range of both synchro- nous and asynchronous applications. max is a registered trademark of altera corporation. warp , warp professional, and warp enterprise are trademarks of cypress semiconductor. macrocell17 macrocell18 macrocell19 macrocell20 macrocell21 macrocell22 macrocell23 macrocell24 macrocell38 macrocell37 macrocell36 macrocell35 macrocell34 macrocell33 9 input 11 input 12 input 13 input p i a macrocell1 macrocell2 macrocell3 macrocell4 macrocell5 macrocell6 macrocell56 macrocell55 macrocell54 macrocell53 macrocell52 macrocell51 macrocell50 macrocell49 macrocells 7?16 macrocells 57?64 macrocells 25?32 macrocells 39?48 input 35 input/clk 34 input 33 input 31 2 4 5 6 7 8 1 44 42 41 40 39 38 37 30 29 28 27 26 24 system clock (3, 14, 25, 36) (10, 21, 32, 43) v cc gnd lab a lab b lab d lab c c343-1 logic block diagram dedicated inputs i/o pins 15 16 17 18 19 20 22 23 i/o pins i/o pins i/o pins
cy7c343 2 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. ? 65 c to+150 c ambient temperature with power applied ................................................... 0 c to+70 c maximum junction temperature (under bias)................................................................. 150 c supply voltage to ground potential ............... ? 2.0v to +7.0v maximum power dissipation...................................2500 mw dc v cc or gnd current ............................................ 500 ma dc output current, per pin ...................... ? 25 ma to +25 ma dc input voltage [1] ......................................... ? 3.0v to +7.0v dc program voltage..................................................... 13.0v static discharge voltage ........................................... >1100v (per mil ? std ? 883, method 3015) note: 1. minimum dc input is ? 0.3v. during transitions, the inputs may undershoot to ? 2.0v for periods less than 20 ns. selection guide 7c343-20 7c343-25 7c343-30 7c343-35 maximum access time (ns) 20 25 30 35 maximum operating current (ma) commercial 135 135 135 135 military 225 225 225 225 industrial 225 225 225 225 maximum standby current (ma) commercial 125 125 125 125 military 200 200 200 200 industrial 200 200 200 200 pin configuration i/o 4 53 10 11 9 8 7 36 35 37 38 39 19 18 20 12 13 34 33 21 21 22 hlcc, plcc top view 17 16 15 14 23 24 26 25 27 28 29 30 31 32 44 43 41 42 40 v cc gnd i/o i/o i/o v cc input input/clk input gnd input i/o i/o v cc gnd i/o c343-2 6 7c343 i/o i/o i/o i/o i/o i/o i/o i/o input gnd v cc input input input i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o operating range range ambient temperature v cc commercial 0 c to +70 c 5v 5% industrial ? 40 c to +85 c 5v 10% military ? 55 c to +125 c (case) 5v 10%
cy7c343 3 notes: 2. typical values are for t a = 25 c and v cc = 5v. 3. not more than one output should be tested at a time. duration of the short circuit should not be more than one second. v out = 0.5v has been chosen to avoid test problems caused by tester ground degradation. 4. guaranteed but not 100% tested. 5. measured with device programmed as a 16-bit counter in each lab. this parameter is tested periodically by sampling production material. 6. part (a) in ac test load and waveforms is used for all parameters except t er and t xz , which is used for part (b) in ac test load and waveforms. all external timing parameters are measured referenced to external pins of the device. electrical characteristics over the operating range [2] parameter description test conditions min. max. unit v oh output high voltage v cc = min., i oh = ? 4.0 ma 2.4 v v ol output low voltage v cc = min., i ol = 8 ma 0.45 v v ih input high level 2.2 v cc +0.3 v v il input low level ? 0.3 0.8 v i ix input current gnd < v in < v cc ? 10 +10 a i oz output leakage current v o = v cc or gnd ? 40 +40 a i os output short circuit current v cc = max., v out = 0.5v [3, 4] ? 30 ? 90 ma i cc1 power supply current (standby) v i = v cc or gnd (no load) commercial 125 ma military/industrial 200 ma i cc2 power supply current [5] v i = v cc or gnd (no load) f = 1.0 mhz [4, 5] commercial 135 ma military/industrial 225 ma t r recommended input rise time 100 ns t f recommended input fall time 100 ns capacitance [6] parameter description test conditions max. unit c in input capacitance v in = 2v, f = 1.0 mhz 10 pf c out output capacitance v out = 2.0v, f = 1.0 mhz 10 pf ac test loads and waveforms [6] 3.0v 5v output r1 464 ? r2 250 ? 50 pf including jig and scope gnd 90% 10% 90% 10% <6ns <6 ns 5v output r1 464 ? r2 250 ? 5pf including jig and scope (a) (b) output 1.75v equivalent to: th venin equivalent (commercial/military) all input pulses c343-3 c343-4 163 ?
cy7c343 4 programmable interconnect array the programmable interconnect array (pia) solves intercon- nect limitations by routing only the signals needed by each logic array block. the inputs to the pia are the outputs of every macrocell within the device and the i/o pin feedback of every pin on the device. unlike masked or programmable gate arrays, which induce variable delay dependent on routing, the pia has a fixed delay. this eliminates undesired skews among logic signals, which may cause glitches in internal or external logic. the fixed delay, regardless of programmable interconnect array configuration, simplifies design by ensuring that internal signal skews or rac- es are avoided. the result is simpler design implementation, often in a single pass, without the multiple internal logic place- ment and routing iterations required for a programmable gate array to achieve design timing objectives. timing delays timing delays within the cy7c343 may be easily determined using warp ? , warp professional ? , or warp enterprise ? software. the cy7c343 has fixed internal delays, allowing the user to determine the worst case timing delays for any design. design recommendations operation of the devices described herein with conditions above those listed under ? maximum ratings ? may cause per- manent damage to the device. this is a stress rating only and functional operation of the device at these or any other condi- tions above those indicated in the operational sections of this data sheet is not implied. exposure to absolute maximum rat- ings conditions for extended periods of time may affect device reliability. the cy7c343 contains circuitry to protect device pins from high static voltages or electric fields; however, nor- mal precautions should be taken to avoid applying any voltage higher than maximum rated voltages. for proper operation, input and output pins must be con- strained to the range gnd < (v in or v out ) < v cc . unused inputs must always be tied to an appropriate logic level (either v cc or gnd). each set of v cc and gnd pins must be connect- ed together directly at the device. power supply decoupling capacitors of at least 0.2 f must be connected between v cc and gnd. for the most effective decoupling, each v cc pin should be separately decoupled to gnd, directly at the device. decoupling capacitors should have good frequency response, such as monolithic ceramic types. timing considerations unless otherwise stated, propagation delays do not include expanders. when using expanders, add the maximum ex- pander delay t exp to the overall delay. similarly, there is an additional t pia delay for an input from an i/o pin when com- pared to a signal from a straight input pin. when calculating synchronous frequencies, use t s1 if all inputs are on the input pins. t s2 should be used if data is applied at an i/o pin. if t s2 is greater than t co1 , 1/t s2 becomes the limiting frequency in the data path mode unless 1/(t wh + t wl ) is less than 1/t s2 . when expander logic is used in the data path, add the appro- priate maximum expander delay, t exp to t s1 . determine which of 1/(t wh + t wl ), 1/t co1 , or 1/(t exp + t s1 ) is the lowest frequen- cy. the lowest of these frequencies is the maximum data path frequency for the synchronous configuration. when calculating external asynchronous frequencies, use t as1 if all inputs are on dedicated input pins. if any data is applied to an i/o pin, t as2 must be used as the required set-up time. if (t as2 + t ah ) is greater than t aco1 , 1/(t as2 + t ah ) be- comes the limiting frequency in the data path mode unless 1/(t awh + t ah ) is less than 1/(t as2 + t ah ). when expander logic is used in the data path, add the appro- priate maximum expander delay, t exp to t as1 . determine which of 1/(t awh + t awl ), 1/t aco1 , or 1/(t exp + t as1 ) is the lowest frequency. the lowest of these frequencies is the maximum data path frequency for the asynchronous configuration. the parameter t oh indicates the system compatibility of this device when driving other synchronous logic with positive in- put hold times, which is controlled by the same synchronous clock. if t oh is greater than the minimum required input hold time of the subsequent synchronous logic, then the devices are guaranteed to function properly with a common synchro- nous clock under worst-case environmental and supply volt- age conditions. the parameter t aoh indicates the system compatibility of this device when driving subsequent registered logic with a posi- tive hold time and using the same clock as the cy7c343. in general, if t aoh is greater than the minimum required input hold time of the subsequent logic (synchronous or asynchro- nous), then the devices are guaranteed to function properly under worst-case environmental and supply voltage condi- tions, provided the clock signal source is the same. this also applies if expander logic is used in the clock signal path of the driving device, but not for the driven device. this is due to the expander logic in the second device ? s clock signal path adding an additional delay (t exp ), causing the output data from the preceding device to change prior to the arrival of the clock signal at the following device ? s register.
cy7c343 5 figure 1. cy7c343 internal timing model. logic array control delay t lac expander delay t exp clock delay t ic t rd t comb t latch input delay t in pia delay t pia register output delay t od t xz t zx logic array delay t lad feedback delay t fd i/o delay t io input/ output input c343-5 system clock delay t ics t rh t rsu t pre t clr
cy7c343 6 external synchronous switching characteristics [6] over operating range parameter description 7c343-20 7c343-25 unit min. max. min. max. t pd1 dedicated input to combinatorial output delay [7] com ? l/ind 20 25 ns mil 20 25 t pd2 i/o input to combinatorial output delay [8] com ? l/ind 32 39 ns mil 32 39 t pd3 dedicated input to combinatorial output delay with expander delay [9] com ? l/ind 30 37 ns mil 30 37 t pd4 i/o input to combinatorial output delay with expander delay [4, 10] com ? l/ind 42 51 ns 42 51 t ea input to output enable delay [4, 7] com ? l/ind 20 25 ns mil 20 25 t er input to output disable delay [4, 7] com ? l/ind 20 25 ns mil 20 25 t co1 synchronous clock input to output delay com ? l/ind 12 14 ns mil 12 14 t co2 synchronous clock to local feedback to combinatorial output [4, 11] com ? l/ind 25 30 ns mil 30 t s1 dedicated input or feedback set-up time to synchronous clock input [7] com ? l/ind 12 15 ns mil 15 t s2 i/o input set-up time to synchronous clock input [7, 12] com ? l/ind 24 30 ns mil 24 30 t h input hold time from synchronous clock input [7] com ? l/ind 0 0 ns mil 0 0 t wh synchronous clock input high time com ? l/ind 6 8 ns mil 6 8 t wl synchronous clock input low time com ? l/ind 6 8 ns mil 6 8 t rw asynchronous clear width [4, 7] com ? l/ind 20 25 ns mil 20 25 t rr asynchronous clear recovery time [4, 7] com ? l/ind 20 25 ns mil 20 25 t ro asynchronous clear to registered output delay [7] com ? l/ind 20 25 ns mil 20 25 t pr asynchronous preset recovery time [4, 7] com ? l/ind 20 25 ns mil 20 25 t po asynchronous preset to registered output delay [7] com ? l/ind 20 25 ns mil 20 25 t cf synchronous clock to local feedback input [4, 13] com ? l/ind 3 3 ns mil 3 3 t p external synchronous clock period (1/f max3 ) [4] com ? l/ind 12 16 ns mil 12 16
cy7c343 7 f max1 external maximum frequency (1/(t co1 + t s1 )) [4, 14] com ? l/ind 41.6 34 mhz mil 41.6 34 f max2 internal local feedback maximum frequen- cy, lesser of (1/(t s1 + t cf )) or (1/t co1 ) [4, 15] com ? l/ind 66.6 55 mhz mil 66.6 55 f max3 data path maximum frequency, least of 1/(t wl + t wh ), 1/(t s1 + t h ), or (1/t co1 ) [4, 16] com ? l/ind 83.3 62.5 mhz mil 83.3 62.5 f max4 maximum register toggle frequency (1/(t wl +t wh )) [4, 17] com ? l/ind 83.3 62.5 mhz mil 83.3 62.5 t oh output data stable time from synchronous clock input [4, 18] com ? l/ind 3 3 ns mil 3 3 t pw asynchronous preset width [4, 7] com ? l/ind 20 25 ns mil 20 25 notes: 7. this specification is a measure of the delay from input signal applied to a dedicated input (44-pin plcc input pin 9, 11, 12, 13, 31, 33, 34, or 35) to combinatorial output on any output pin. this delay assumes no expander terms are used to form the logic function. when this note is applied t o any parameter specification it indicates that the signal (data, asynchronous clock, asynchronous clear, and/or asynchronous preset) is applied to a dedicat ed input only and no signal path (either clock or data) employs expander logic. if an input signal is applied to an i/o pin, an additional delay equal to t pia should be added to the comparable delay for a dedicated input. if ex panders are used, add the maximum expander delay t exp to the overall delay for the comparable delay without expanders. 8. this specification is a measure of the delay from input signal applied to an i/o macrocell pin to any output. this delay assu mes no expander terms are used to form the logic function. 9. this specification is a measure of the delay from an input signal applied to a dedicated input (44-pin plcc input pin 9, 11, 12, 13, 31, 33, 34, or 35) to combinatorial output on any output pin. this delay assumes expander terms are used to form the logic function and includes the worst-case expander logic delay for one pass through the expander logic. this parameter is tested periodically by sampling production material. 10. this specification is a measure of the delay from an input signal applied to an i/o macrocell pin to any output. this delay assumes expander terms are used to form the logic function and includes the worst-case expander logic delay for one pass through the expander logic. this param eter is tested periodically by sampling production material. 11. this specification is a measure of the delay from synchronous register clock to internal feedback of the register output sig nal to the input of the lab logic array and then to a combinatorial output. this delay assumes no expanders are used, register is synchronously clocked and all f eedback is within the same lab. this parameter is tested periodically by sampling production material. 12. if data is applied to an i/o input for capture by a macrocell register, the i/o pin set-up time minimums should be observed. these parameters are t s2 for synchronous operation and t as2 for asynchronous operation. 13. this specification is a measure of the delay associated with the internal register feedback path. this is the delay from syn chronous clock to lab logic array input. this delay plus the register set-up time, t s1 , is the minimum internal period for an internal synchronous state machine configuration. this delay is for feedback within the same lab. this parameter is tested periodically by sampling production material. 14. this specification indicates the guaranteed maximum frequency, in synchronous mode, at which a state machine configuration w ith external feedback can operate. it is assumed that all data inputs and feedback signals are applied to dedicated inputs. 15. this specification indicates the guaranteed maximum frequency at which a state machine, with internal-only feedback, can ope rate. if register output states must also control external points, this frequency can still be observed as long as this frequency is less than 1/t co1 . all feedback is assumed to be local, originating within the same lab.. 16. this frequency indicates the maximum frequency at which the device may operate in data path mode. this delay assumes data in put signals are applied to dedicated inputs and no expander logic is used. 17. this specification indicates the guaranteed maximum frequency, in synchronous mode, at which an individual output or buried register can be cycled. 18. this parameter indicates the minimum time after a synchronous register clock input that the previous register output data is maintained on the output pin. external synchronous switching characteristics [6] over operating range (continued) parameter description 7c343-20 7c343-25 unit min. max. min. max.
cy7c343 8 external synchronous switching characteristics [6] over operating range (continued) parameter description 7c343-30 7c343-35 unit min. max. min. max. t pd1 dedicated input to combinatorial output delay [7] com ? l/ind 30 35 ns mil 30 35 t pd2 i/o input to combinatorial output delay [8] com ? l/ind 44 53 ns mil 44 53 t pd3 dedicated input to combinatorial output delay with expander delay [9] com ? l/ind 44 55 ns mil 44 55 t pd4 i/o input to combinatorial output delay with expander delay [4, 10] com ? l/ind 58 73 ns mil 58 73 t ea input to output enable delay [4, 7] com ? l/ind 30 35 ns mil 30 35 t er input to output disable delay [4, 7] com ? l/ind 30 35 ns mil 30 35 t co1 synchronous clock input to output delay com ? l/ind 16 20 ns mil 16 20 t co2 synchronous clock to local feedback to combinatorial output [4, 11] com ? l/ind 35 42 ns mil 35 42 t s1 dedicated input or feedback set-up time to synchronous clock input [7] com ? l/ind 20 25 ns mil 20 25 t s2 i/o input set-up time to synchronous clock input [7, 12] com ? l/ind 35 42 ns mil 35 42 t h input hold time from synchronous clock input [7] com ? l/ind 0 0 ns mil 0 0 t wh synchronous clock input high time com ? l/ind 10 12.5 ns mil 10 12.5 t wl synchronous clock input low time com ? l/ind 10 12.5 ns mil 10 12.5 t rw asynchronous clear width [4, 7] com ? l/ind 30 35 ns mil 30 35 t rr asynchronous clear recovery time [4, 7] com ? l/ind 30 35 ns mil 30 35 t ro asynchronous clear to registered output delay [7] com ? l/ind 30 35 ns mil 30 35 t pr asynchronous preset recovery time [4, 7] com ? l/ind 30 35 ns mil 30 35 t po asynchronous preset to registered output delay [7] com ? l/ind 30 35 ns mil 30 35 t cf synchronous clock to local feedback input [4, 13] com ? l/ind 3 5 ns mil 3 5 t p external synchronous clock period (1/f max3 ) [4] com ? l/ind 20 25 ns mil 20 25
cy7c343 9 f max1 external maximum frequency (1/(t co1 + t s1 )) [4, 14] com ? l/ind 27 22.2 mhz mil 27 22.2 f max2 internal local feedback maximum frequen- cy, lesser of (1/(t s1 + t cf )) or (1/t co1 ) [4, 15] com ? l/ind 43 33 mhz mil 43 33 f max3 data path maximum frequency, least of 1/(t wl + t wh ), 1/(t s1 + t h ), or (1/t co1 ) [4, 16] com ? l/ind 50 40 mhz mil 50 40 f max4 maximum register toggle frequency (1/(t wl +t wh )) [4, 17] com ? l/ind 50 40 mhz mil 50 40 t oh output data stable time from synchronous clock input [4, 18] com ? l/ind 3 3 ns mil 3 3 t pw asynchronous preset width [4, 7] com ? l/ind 30 35 ns mil 30 35 external synchronous switching characteristics [6] over operating range (continued) parameter description 7c343-30 7c343-35 unit min. max. min. max. external asynchronous switching characteristics over operating range [6] parameter description 7c343-20 7c343-25 unit min. max. min. max. t aco1 asynchronous clock input to output delay [7] com ? l/ind 20 12 ns mil 20 t aco2 asynchronous clock input to local feedback to combinatorial output [19] com ? l/ind 32 25 ns mil 32 25 t as1 dedicated input or feedback set-up time to asynchronous clock input [7] com ? l/ind 4 40 ns mil 4 40 t as2 i/o input set-up time to asynchronous clock input [7] com ? l/ind 15 5 ns mil 15 5 t ah input hold time from asynchronous clock input [7] com ? l/ind 5 20 ns mil 5 20 t awh asynchronous clock input high time [7] com ? l/ind 9 6 ns mil 9 6 t awl asynchronous clock input low time [7, 20] com ? l/ind 7 11 ns mil 7 11 t acf asynchronous clock to local feedback input [4, 21] com ? l/ind 13 9 ns mil 13 9 t ap external asynchronous clock period (1/f maxa4 ) [4] com ? l/ind 16 15 ns mil 16 15 f maxa1 external maximum frequency in asynchro- nous mode 1/(t aco1 + t as1 ) [4, 22] com ? l/ind 41.6 20 mhz mil 41.6 20 f maxa2 maximum internal asynchronous frequency [4, 23] com ? l/ind 58.8 33 mhz mil 58.8 50 f maxa3 data path maximum frequency in asynchro- nous mode [4, 24] com ? l/ind 50 50 mhz mil 50
cy7c343 10 f maxa4 maximum asynchronous register toggle frequency 1/(t awh + t awl ) [4, 25] com ? l/ind 62.5 40 mhz mil 62.5 40 t aoh output data stable time from asynchronous clock input [4, 26] com ? l/ind 12 15 ns mil 12 15 notes: 19. this specification is a measure of the delay from an asynchronous register clock input to internal feedback of the register output signal to the input of the lab logic array and then to a combinatorial output. this delay assumes no expanders are used in the logic of combinatorial output o r the asynchronous clock input. the clock signal is applied to a dedicated input pin and all feedback is within a single lab. this parameter is tested periodic ally by sampling production material. 20. this parameter is measured with a positive-edge triggered clock at the register. for negative edge triggering, the t awh and t awl parameters must be swapped. if a given input is used to clock multiple registers with both positive and negative polarity, t awh should be used for both t awh and t awl . 21. this specification is a measure of the delay associated with the internal register feedback path for an asynchronous clock t o lab logic array input. this delay plus the asynchronous register set-up time, t as1 , is the minimum internal period for an internal asynchronously clocked state machine configuration. this delay is for feedback within the same lab, assumes no expander logic in the clock path, and assumes that the clock input signal is applied t o a dedicated input pin. this parameter is tested periodically by sampling production material. 22. this specification indicates the guaranteed maximum frequency at which an asynchronously clocked state machine configuration with external feedback can operate. it is assumed that all data inputs, clock inputs, and feedback signals are applied to dedicated inputs, and that no ex pander logic is employed in the clock signal path or data path. 23. this specification indicates the guaranteed maximum frequency at which an asynchronously clocked state machine with internal -only feedback can operate. this parameter is determined by the lesser of (1/t acf + t as1 )) or (1/(t awh +t awl )). if register output states must also control external points, this frequency can still be observed as long as this frequency is less than 1/t aco1 . 24. this frequency is the maximum frequency at which the device may operate in the asynchronously clocked data path mode. this s pecification is determined by the least of 1/(t awh + t awl ), 1/(t as1 + t ah ) or 1/t aco1 . it assumes data and clock input signals are applied to dedicated input pins and no expander logic is used. 25. this specification indicates the guaranteed maximum frequency at which an individual output or buried register can be cycled in asynchronously clocked mode by a clock signal applied to an external dedicated input pin. 26. this parameter indicates the minimum time that the previous register output data is maintained on the output after an asynch ronous register clock input. external asynchronous switching characteristics over operating range [6] (continued) parameter description 7c343-20 7c343-25 unit min. max. min. max. external asynchronous switching characteristics over operating range [6] parameter description 7c343-30 7c343-35 unit min. max. min. max. t aco1 asynchronous clock input to output delay [7] com ? l/ind 30 35 ns mil 30 35 t aco2 asynchronous clock input to local feedback to combinatorial output [19] com ? l/ind 46 55 ns mil 46 55 t as1 dedicated input or feedback set-up time to asynchronous clock input [7] com ? l/ind 6 8ns mil 6 8 t as2 i/o input set-up time to asynchronous clock input [7] com ? l/ind 25 30 ns mil 25 30 t ah input hold time from asynchronous clock input [7] com ? l/ind 8 10 ns mil 8 10 t awh asynchronous clock input high time [7] com ? l/ind 14 16 ns mil 14 16 t awl asynchronous clock input low time [7, 20] com ? l/ind 11 14 ns mil 11 14 t acf asynchronous clock to local feedback input [4, 21] com ? l/ind 18 22 ns mil 18 22 t ap external asynchronous clock period (1/f maxa4 ) [4] com ? l/ind 25 30 ns mil 25 30 f maxa1 external maximum frequency in asynchro- nous mode 1/(t aco1 + t as1 ) [4, 22] com ? l/ind 27 23 mhz mil 27 23
cy7c343 11 f maxa2 maximum internal asynchronous frequency [4, 23] com ? l/ind 40 33 mhz mil 40 33 f maxa3 data path maximum frequency in asynchronous mode [4, 24] com ? l/ind 33 28 mhz mil 33 28 f maxa4 maximum asynchronous register toggle frequency 1/(t awh + t awl ) [4, 25] com ? l/ind 40 33 mhz mil 40 33 t aoh output data stable time from asynchronous clock input [4, 26] com ? l/ind 15 15 ns mil 15 15 internal switching characteristics over operating range [6] parameter description 7c343-20 7c343-25 unit min. max. min. max. t in dedicated input pad and buffer delay com ? l/ind 4 5 ns mil 4 5 t io i/o input pad and buffer delay com ? l/ind 4 5 ns mil 4 5 t exp expander array delay com ? l/ind 10 12 ns mil 10 12 t lad logic array data delay com ? l/ind 10 12 ns mil 10 12 t lac logic array control delay com ? l/ind 8 10 ns mil 8 10 t od output buffer and pad delay com ? l/ind 4 5 ns mil 4 5 t zx output buffer enable delay [27] com ? l/ind 8 10 ns mil 8 10 t xz output buffer disable delay com ? l/ind 8 10 ns mil 8 10 t rsu register set-up time relative to clock signal at register com ? l/ind 4 6 ns mil 4 6 t rh register hold time relative to clock signal at register com ? l/ind 4 6 ns mil 4 6 t latch flow-through latch delay com ? l/ind 2 3 ns mil 2 3 t rd register delay com ? l/ ind 1 1 ns mil 1 1 t comb transparent mode delay [28] com ? l/ind 2 3 ns mil 2 3 external asynchronous switching characteristics over operating range [6] (continued) parameter description 7c343-30 7c343-35 unit min. max. min. max.
cy7c343 12 t ch clock high time com ? l/ind 6 8 ns mil 6 8 t cl clock low time com ? l/ind 6 8 ns mil 6 8 t ic asynchronous clock logic delay com ? l/ind 12 14 ns mil 12 14 t ics synchronous clock delay com ? l/ind 2 2 ns mil 2 2 t fd feedback delay com ? l/ind 1 1 ns mil 1 1 t pre asynchronous register preset time com ? l/ind 4 5 ns mil 4 5 t clr asynchronous register clear time com ? l/ind 4 5 ns mil 4 5 t pcw asynchronous preset and clear pulse width com ? l /ind 4 5 ns mil 4 5 t pcr asynchronous preset and clear recovery time com ? l/ind 4 5 ns mil 4 5 t pia programmable interconnect array delay time com ? l/ind 12 14 ns mil 12 14 notes: 27. sample tested only for an output change of 500 mv. 28. this specification guarantees the maximum combinatorial delay associated with the macrocell register bypass when the macroce ll is configured for combi- natorial operation. internal switching characteristics over operating range [6] (continued) parameter description 7c343-20 7c343-25 unit min. max. min. max. internal switching characteristics over operating range [6] parameter description 7c343-30 7c343-35 min. max. min. max. unit t in dedicated input pad and buffer delay com ? l/ind 7 9 ns mil 7 9 t io i/o input pad and buffer delay com ? l/ind 5 7 ns mil 5 7 t exp expander array delay com ? l/ind 14 20 ns mil 14 20 t lad logic array data delay com ? l/ind 14 16 ns mil 14 16 t lac logic array control delay com ? l/ind 12 13 ns mil 12 13 t od output buffer and pad delay com ? l/ind 5 6 ns mil 5 6
cy7c343 13 t zx output buffer enable delay [27] com ? l/ind 11 13 ns mil 11 13 t xz output buffer disable delay com ? l/ind 11 13 ns mil 11 13 t rsu register set-up time relative to clock signal at register com ? l/ind 8 10 ns mil 8 10 t rh register hold time relative to clock signal at register com ? l/ind 8 12 ns mil 8 12 t latch flow-through latch delay com ? l/ind 4 4 ns mil 4 4 t rd register delay com ? l/ind 2 2 ns mil 2 2 t comb transparent mode delay [28] com ? l/ind 4 4 ns mil 4 4 t ch clock high time com ? l/ind 10 12.5 ns mil 10 12.5 t cl clock low time com ? l/ind 10 12.5 ns mil 10 12.5 t ic asynchronous clock logic delay com ? l/ind 16 18 ns mil 16 18 t ics synchronous clock delay com ? l/ind 2 3 ns mil 2 3 t fd feedback delay com ? l/ind 1 2 ns mil 1 2 t pre asynchronous register preset time com ? l/ind 6 7 ns mil 6 7 t clr asynchronous register clear time com ? l/ind 6 7 ns mil 6 7 t pcw asynchronous preset and clear pulse width com ? l/ind 6 7 ns mil 6 7 t pcr asynchronous preset and clear recovery time com ? l/ind 6 7 ns mil 6 7 t pia programmable interconnect array delay time com ? l/ind 16 20 ns mil 16 20 internal switching characteristics over operating range [6] (continued) parameter description 7c343-30 7c343-35 min. max. min. max. unit
cy7c343 14 switching waveforms external combinatorial t pd1 /t pd2 t er valid output dedicated input/ i/o input combinatorial output combinatorial or registered c343-6 high-impedance three-state high-impedance three ? state output t er external synchronous t h t s1 t wh t wl t rr /t pr t rw /t pw t oh t co1 t ro /t po t co2 c343-7 dedicated inputs or registered feedback synchronous clock asynchronous clear/preset registered outputs combinatorial output from registered feedback [7] [7] [11] t aco1 external asynchronous t ah t as1 t awh t awl t rr /t pr t rw /t pw t aoh t ro /t po t aco2 asynchronous clock input asynchronous registered outputs dedicatedinputsor registered feedback asynchronous clear/preset combinatorial output from asynch. registered feedback [7 ] [7 ] c343-8
cy7c343 15 switching waveforms (continued) internal combinatorial t in t io t pia t exp t lac ,t lad input pin expander i/o pin logic array array delay output logic array input c343-9 internal asynchronous t io t awh t awl t f t in t ic t rsu t rh t rd ,t latch t fd t clr ,t pre t fd clock pin logic array logic array clock from data from clock into logic array to local lab register output t r c343-10 internal synchronous t ch t cl t in t ics t rsu t rh c343-12 system clock pin system clock at register data from logic array
cy7c343 16 military specifications group a subgroup testing document #: 38-00128-j switching waveforms (continued) output mode c343-11 t xz t zx t od high impedance state clock from logic array logic array data from output pin t rd ordering information speed (ns) ordering code package name package type operating range 20 cy7c343-20jc/ji j67 44-lead plastic leaded chip carrier commercial/industrial 25 cy7c343-25hc/hi h67 44-pin windowed leaded chip carrier commercial/industrial CY7C343-25JC/ji j67 44-lead plastic leaded chip carrier 30 cy7c343-30hc/hi h67 44-pin windowed leaded chip carrier commercial/industrial cy7c343-30jc/ji j67 44-lead plastic leaded chip carrier cy7c343-30hmb h67 44-pin windowed leaded chip carrier military 35 cy7c343-35hc/hi h67 44-pin windowed leaded chip carrier commercial/industrial cy7c343-35jc j67 44-lead plastic leaded chip carrier cy7c343-35hmb h67 44-pin windowed leaded chip carrier military dc characteristics parameters subgroups v oh 1, 2, 3 v ol 1, 2, 3 v ih 1, 2, 3 v il 1, 2, 3 i ix 1, 2, 3 i oz 1, 2, 3 i cc1 1, 2, 3 switching characteristics parameters subgroups t pd1 7, 8, 9, 10, 11 t pd2 7, 8, 9, 10, 11 t pd3 7, 8, 9, 10, 11 t co1 7, 8, 9, 10, 11 t s 7, 8, 9, 10, 11 t h 7, 8, 9, 10, 11 t aco1 7, 8, 9, 10, 11 t aco2 7, 8, 9, 10, 11 t as 7, 8, 9, 10, 11 t ah 7, 8, 9, 10, 11
cy7c343 17 package diagrams 44-pin windowed leaded chip carrier h67 51-80079
cy7c343 ? cypress semiconductor corporation, 2000. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. package diagrams (continued) 44-lead plastic leaded chip carrier j67 51-85003-a

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